The invention relates to an integrated circuit for asynchronous serial data transfer, and in particular to an integrated circuit for an asynchronous serial data transfer with a bit length counter.
In a communications system composed of one or more transmitters and receivers, data are transmitted such the transfer speed or transfer rate is defined by the number of transferred bits per second, or by the reciprocal thereof, the duration of a bit.
A transfer is termed “serial” when the individual bits are transferred between a transmitter and a receiver in succession. A transfer is termed “asynchronous” when no clock signal is transmitted with the data between the transmitter and the receiver, which would enable a synchronous sampling of the individual bits in the receiver. With an asynchronous transfer, a receiver must accordingly detect a synchronization character sent at the beginning of a transmission, and starting therefrom must calculate the sampling instants for the subsequent data bits. To this end, the receiver must be able to precisely adjust the time period for the transfer of one bit, that is, the bit length. Generally, a receiver can only set bit lengths that match an integer number of clock cycles of a separate clock generator or oscillator. For this reason, the receiver can only set a desired transfer rate with a limited precision. This theoretically attainable precision depends, among other factors, on the ratio of the transfer rate to the frequency of the oscillator. The theoretically attainable precision G1 is calculated by:G1=U/F×100where G1 is the fundamentally or theoretically attainable precision as a percentage, U is the transfer rate in bits/s, and F is the frequency of the oscillator in Hz.
FIG. 4 illustrates a receiver 400 for serial data streams of an asynchronous transfer. A system clock sclk on a line 402 is applied by an oscillator 403 to an adjustable prescaler 404 to divide the system clock sclk on the line 402 by the divisor n. The adjustable prescaler 404 outputs a corresponding sampling clock aclk on a line 406. The sampling clock on the line 406 is applied to a fixed bit length counter 408 and a sampler 410. In addition, a sequence of serial data d on a line 412 is applied to the sampler 410 which are sampled by the sampling clock aclk on the line 406. The sampler 410 outputs a corresponding bit level blev on a line 414 to a bit omnibus circuit 416. The fixed bit length counter 408 divides the applied sampling clock aclk on the line 406 by, for example, the fixed set value 16 and outputs a corresponding bit clock bclk on a line 418 to the bit omnibus circuit 416. The bit omnibus circuit 416 generates a corresponding output signal or output data o on a line 420 which are applied to an output of the receiver.
This type of receiver for asynchronous serial data subdivides the bit time into a fixed number of sampling clock cycles, for example, 8 or 16 clock cycles per bit. The sampling clock aclk on the 406 is derived by the adjustable prescaler 404 from the system clock sclk. What is adjustable here is the division to be performed by the prescaler 404 to supply the desired sampling clock aclk. However, the number of clock cycles per bit is defined by the hardware, that is, by the structural design of the fixed bit length counter 408 of a corresponding integrated circuit. The prescaler 404 can generally be loaded only with integer divisors n. These requirements—a fixed number of clock cycles per bit and integer divisors n for the prescaler 404—limit the attainable precision. The precision here depends on the ratio of the transfer rate to the frequency of the oscillator 403 divided by the number of clock cycles per bit. The attainable precision corresponds to:G2=(U×TpB)/F×100where G2 is the attainable precision as a percentage, U is the transfer rate in bits/s, TpB is the number of clock cycles per bit, for example, 8 or 16, and F is the frequency of the oscillator in Hz.
Correspondingly, the bit length immediately changes by 8 or 16 oscillator cycles when the divisor of the prescaler 404 is changed by 1. A convergence on a desired bit length can only be implemented in increments of 8 or 16 oscillator cycles, thereby resulting in the worst case in an erroneous determination of 4 or 8 oscillator cycles.
A receiver for asynchronous serial data transfers to which a baud rate generator for supplying two different clocks is connected on the input side is known from ARM PrimeCell UART(PL011), Technical Reference Manual, 2001. A receiver in which one of two different clocks is selectable is known from DesignWare DW_apb_uart Databook, chapter 1: Description of DW_apb_uart, 2003. This presupposes explicit limits for reception. A programmable baud rate generator is known from National Semiconductor, PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs, June 1995. A programmable baud rate generator which generates a baud rate clock and a receiver reference clock is known from QuickLogic Corporation, Open Source 16550 UART Core, Application Note 69, 2002.
What is disadvantageous in all receivers is the large increment width of 8 or 16 oscillator cycles. The result of this is that at a specific oscillator frequency certain transfer rates cannot be set with the required precision. For example, a transfer rate of U=20 kbits/s, and oscillator frequency of F=4 MHz, and a bit length of TpB=8 cycles results in an attainable precision of G2=20000/4000000×8×100=4%. This kind of error, however, is not tolerable in many applications.
To reduce this large increment width of normally 8 or 16 cycles, and thus the maximum residual error, a technique is employed which is called a “fractional prescaler,” by which is meant a prescaler which at specific intervals lengthens or shortens a sampling clock by one oscillator cycle. As a result, one or more of the 8 or 16 sampling clocks per bit is lengthened or shortened by one oscillator cycle. Aside from the considerable complexity in terms of methodological technique, there is also the additional factor that implementation of the hardware structures is costly.
A known alternative approach is to influence the oscillator such that its output frequency no longer remains constant, but becomes sometimes faster, sometimes slower, depending on the requirement of the receiver. Such a solution is precluded, however, in systems in which other modules are dependent on a constant oscillator clock, or when two of the described receivers must operate at different transfer rates and are supplied by one common oscillator clock.
There is a need for an improved asynchronous serial data transfer.